Resolving p-type transistor drain saturation current (IDsat) off-target issue for 0.3um logic device

Resolving p-type transistor drain saturation current (IDsat) off-target issue for 0.3um logic device

Transistor optimization is required for good device performance especially on those devices with off-center electrical se (ET) specifications. In this thesis, the author explores various possible options to bring a particular 0.3?m device Logic Dual gate oxide PMOS transistor IDsat to electrical tes...

Full description

Saved in:
Bibliographic Details
Main Author: Tan, Ai Kiam
Other Authors: Zhang, Dao Hua
Format: Theses and Dissertations
Published: 2008
Subjects:
DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Online Access:http://hdl.handle.net/10356/3325
Tags: Add Tag
No Tags, Be the first to tag this record!
Institution: Nanyang Technological University
id sg-ntu-dr.10356-3325
record_format dspace
spelling sg-ntu-dr.10356-33252023-07-04T15:08:33Z Resolving p-type transistor drain saturation current (IDsat) off-target issue for 0.3um logic device Tan, Ai Kiam Zhang, Dao Hua School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Transistor optimization is required for good device performance especially on those devices with off-center electrical se (ET) specifications. In this thesis, the author explores various possible options to bring a particular 0.3?m device Logic Dual gate oxide PMOS transistor IDsat to electrical test target so as to ensure optimum device performance and yield. Master of Science (Microelectronics) 2008-09-17T09:27:26Z 2008-09-17T09:27:26Z 2002 2002 Thesis http://hdl.handle.net/10356/3325 Nanyang Technological University application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
topic DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
spellingShingle DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Tan, Ai Kiam
Resolving p-type transistor drain saturation current (IDsat) off-target issue for 0.3um logic device
description Transistor optimization is required for good device performance especially on those devices with off-center electrical se (ET) specifications. In this thesis, the author explores various possible options to bring a particular 0.3?m device Logic Dual gate oxide PMOS transistor IDsat to electrical test target so as to ensure optimum device performance and yield.
author2 Zhang, Dao Hua
author_facet Zhang, Dao Hua
Tan, Ai Kiam
format Theses and Dissertations
author Tan, Ai Kiam
author_sort Tan, Ai Kiam
title Resolving p-type transistor drain saturation current (IDsat) off-target issue for 0.3um logic device
title_short Resolving p-type transistor drain saturation current (IDsat) off-target issue for 0.3um logic device
title_full Resolving p-type transistor drain saturation current (IDsat) off-target issue for 0.3um logic device
title_fullStr Resolving p-type transistor drain saturation current (IDsat) off-target issue for 0.3um logic device
title_full_unstemmed Resolving p-type transistor drain saturation current (IDsat) off-target issue for 0.3um logic device
title_sort resolving p-type transistor drain saturation current (idsat) off-target issue for 0.3um logic device
publishDate 2008
url http://hdl.handle.net/10356/3325
_version_ 1772825228743802880

Similar Items