Resolving p-type transistor drain saturation current (IDsat) off-target issue for 0.3um logic device

Resolving p-type transistor drain saturation current (IDsat) off-target issue for 0.3um logic device

Transistor optimization is required for good device performance especially on those devices with off-center electrical se (ET) specifications. In this thesis, the author explores various possible options to bring a particular 0.3?m device Logic Dual gate oxide PMOS transistor IDsat to electrical tes...

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Bibliographic Details
Main Author: Tan, Ai Kiam
Other Authors: Zhang, Dao Hua
Format: Theses and Dissertations
Published: 2008
Subjects:
DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Online Access:http://hdl.handle.net/10356/3325
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Institution: Nanyang Technological University
Description
Summary:Transistor optimization is required for good device performance especially on those devices with off-center electrical se (ET) specifications. In this thesis, the author explores various possible options to bring a particular 0.3?m device Logic Dual gate oxide PMOS transistor IDsat to electrical test target so as to ensure optimum device performance and yield.

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