Resolving p-type transistor drain saturation current (IDsat) off-target issue for 0.3um logic device
Transistor optimization is required for good device performance especially on those devices with off-center electrical se (ET) specifications. In this thesis, the author explores various possible options to bring a particular 0.3?m device Logic Dual gate oxide PMOS transistor IDsat to electrical tes...
Saved in:
Main Author: | Tan, Ai Kiam |
---|---|
Other Authors: | Zhang, Dao Hua |
Format: | Theses and Dissertations |
Published: |
2008
|
Subjects: | |
Online Access: | http://hdl.handle.net/10356/3325 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |
Similar Items
-
Process capability index (CPK) improvement for NMOS transistor IDSAT of 0.3 micrometer technology
by: Goh, Beng Lee.
Published: (2008) -
Experimental modules on integrated circuit design using tanner for 0.25 um, 0.35 um, and 0.5 CMOS process
by: Escano, Ron Alvin V., et al.
Published: (2010) -
Spatially resolved emitter saturation current by photoluminescence imaging
by: Hameiri, Z., et al.
Published: (2014) -
Analysis of alu chip and realizing with pass transistor logic
by: U Win Lwin
Published: (2008) -
Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic
by: Ho, Weng-Geng, et al.
Published: (2013)