Design of high performance CMOS latches and flip-flops

Recommend ways to implement the various Double Edge Triggered Flip-Flop (DETFF) so that it can operate at the highest possible clock frequency, low enough operating nominal voltage and less power consumed by exploring various design circuit topologies and coming out with the best one with the curren...

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Bibliographic Details
Main Author:	Tan, Teck Heng.
Other Authors:	Yeo, Kiat Seng
Format:	Theses and Dissertations
Published:	2008
Subjects:	DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Online Access:	http://hdl.handle.net/10356/3390
Tags:	Add Tag No Tags, Be the first to tag this record!
Institution:	Nanyang Technological University

id	sg-ntu-dr.10356-3390
record_format	dspace
spelling	sg-ntu-dr.10356-33902023-07-04T15:51:23Z Design of high performance CMOS latches and flip-flops Tan, Teck Heng. Yeo, Kiat Seng School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Recommend ways to implement the various Double Edge Triggered Flip-Flop (DETFF) so that it can operate at the highest possible clock frequency, low enough operating nominal voltage and less power consumed by exploring various design circuit topologies and coming out with the best one with the current Chartered Semiconductor 0.18 urn and 0.25 urn CMOS technologies. Master of Science (Consumer Electronics) 2008-09-17T09:29:09Z 2008-09-17T09:29:09Z 2004 2004 Thesis http://hdl.handle.net/10356/3390 Nanyang Technological University application/pdf
institution	Nanyang Technological University
building	NTU Library
continent	Asia
country	Singapore Singapore
content_provider	NTU Library
collection	DR-NTU
topic	DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
spellingShingle	DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Tan, Teck Heng. Design of high performance CMOS latches and flip-flops
description	Recommend ways to implement the various Double Edge Triggered Flip-Flop (DETFF) so that it can operate at the highest possible clock frequency, low enough operating nominal voltage and less power consumed by exploring various design circuit topologies and coming out with the best one with the current Chartered Semiconductor 0.18 urn and 0.25 urn CMOS technologies.
author2	Yeo, Kiat Seng
author_facet	Yeo, Kiat Seng Tan, Teck Heng.
format	Theses and Dissertations
author	Tan, Teck Heng.
author_sort	Tan, Teck Heng.
title	Design of high performance CMOS latches and flip-flops
title_short	Design of high performance CMOS latches and flip-flops
title_full	Design of high performance CMOS latches and flip-flops
title_fullStr	Design of high performance CMOS latches and flip-flops
title_full_unstemmed	Design of high performance CMOS latches and flip-flops
title_sort	design of high performance cmos latches and flip-flops
publishDate	2008
url	http://hdl.handle.net/10356/3390
_version_	1772827093043773440

Design of high performance CMOS latches and flip-flops

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