Simulation of stress in advanced silicided device structures

• Main Author: Wong, Michael Hon Weng.
• Other Authors: Pey, Kin Leong
• Format: Theses and Dissertations
• Published: 2008
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Microelectronics
• Online Access: http://hdl.handle.net/10356/3745
• Institution: Nanyang Technological University

In this project, a study of the process-induced stress associated with the silicidation of the poly-Si gate was done. The TSUPREM-4 software was used to simulate the growth of both the Ti- and Co-silicided 0.1 8um gate structures. The stress readings at the top corner of the poly-Si gate and in the silicon region under the edge of the nitride spacer, which were obtained from the simulations, were examined. The stress profiles show that the stress concentrations at these regions are highly compressive. The stress profiles also show a decrease in the magnitudes of the stress contours as the point of interest moves away from the top corner of the poly-Si gate or from the silicon region under the edge of the nitride spacer, and further into the bulk of the poly-Si/Si-substrate. The stress findings show that the stress induced by the silicide layers increase with the thickness of both the Ti or Co layer deposited. It can also be inferred from the stress profiles that the longer the annealing time, the larger will be the magnitude of the stress induced by the silicide layer.