Copper-ultra low k porous SiLK integration for deep submicron integrated circuits

• Main Author: Yang, Lieyong
• Other Authors: P. D. Foo
• Format: Theses and Dissertations
• Published: 2008
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: https://hdl.handle.net/10356/3838
• Institution: Nanyang Technological University

The integration of Cu and ULK porous SiLK using different barriers on blanket and patterned wafers has been investigated. This includes characterizations of ULK porous SiLK, Ta based barrier on ULK structures and Ta(N)/SiCN/ULK SiLK structures, and integration of Cu-ULK porous SiLK with different barriers on blanket and patterned wafers. The thermal stability, interaction and electrical properties of different structures were comparatively investigated by using various techniques. The single damascene lines were fabricated of Cu and ULK porous SiLK with different barrier layers in 0.13 µm technology. The line resistance, line to line leakage and breakdown voltage were evaluated at various conditions. Furthermore, effects of plasma treatment and additional SiCN layer on the electrical performance and thermal stability of the Cu/barrier/ULK structures were evaluated. Finally, the thickness of SiCN was also optimized by comparing the electrical performance of the samples with different SiCN thickness.