Design of a high speed CMOS analog comparator
The comparators are widely used in the process of converting analog signals to discrete signals; as such they are required to perform at high speed. To avoid noise from triggering the comparator wrongly, hysteresis is included. However, in CMOS, offset voltage between input differential pair is quit...
Saved in:
Main Author: | Chen, Qi. |
---|---|
Other Authors: | Siek Liter |
Format: | Final Year Project |
Language: | English |
Published: |
2010
|
Subjects: | |
Online Access: | http://hdl.handle.net/10356/40183 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |
Language: | English |
Similar Items
-
High speed, low jitter CMOS analog PLL for clock recovery application
by: Sudhaleswar Behera.
Published: (2008) -
Design of the low-voltage CMOS analog multiplier
by: Sun, Guoliang.
Published: (2008) -
High speed CMOS multiplier design
by: Tay, Wen Kai
Published: (2022) -
16 bits high speed CMOS multiplier IC design
by: Wut Yee Win Thoung
Published: (2021) -
Design of the low-voltage CMOS analog multiplier
by: Guo, Lizao.
Published: (2012)