Power optimization in data path allocation for high-level synthesis
This thesis addresses the problem of minimizing power consumption in the high-level synthesis of data-dominated CMOS circuits.
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| Format: | Theses and Dissertations |
| Published: |
2008
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| Online Access: | http://hdl.handle.net/10356/4049 |
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| Institution: | Nanyang Technological University |
| Summary: | This thesis addresses the problem of minimizing power consumption in the high-level synthesis of data-dominated CMOS circuits. |
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