Power optimization in data path allocation for high-level synthesis

This thesis addresses the problem of minimizing power consumption in the high-level synthesis of data-dominated CMOS circuits.

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Bibliographic Details
Main Author:	Zheng, Yuhong.
Other Authors:	Jong, Ching Chuen
Format:	Theses and Dissertations
Published:	2008
Subjects:	DRNTU::Engineering::Electrical and electronic engineering::Power electronics
Online Access:	http://hdl.handle.net/10356/4049
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Institution:	Nanyang Technological University

id	sg-ntu-dr.10356-4049
record_format	dspace
spelling	sg-ntu-dr.10356-40492023-07-04T15:20:37Z Power optimization in data path allocation for high-level synthesis Zheng, Yuhong. Jong, Ching Chuen School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Power electronics This thesis addresses the problem of minimizing power consumption in the high-level synthesis of data-dominated CMOS circuits. Master of Engineering 2008-09-17T09:43:13Z 2008-09-17T09:43:13Z 2001 2001 Thesis http://hdl.handle.net/10356/4049 Nanyang Technological University application/pdf
institution	Nanyang Technological University
building	NTU Library
continent	Asia
country	Singapore Singapore
content_provider	NTU Library
collection	DR-NTU
topic	DRNTU::Engineering::Electrical and electronic engineering::Power electronics
spellingShingle	DRNTU::Engineering::Electrical and electronic engineering::Power electronics Zheng, Yuhong. Power optimization in data path allocation for high-level synthesis
description	This thesis addresses the problem of minimizing power consumption in the high-level synthesis of data-dominated CMOS circuits.
author2	Jong, Ching Chuen
author_facet	Jong, Ching Chuen Zheng, Yuhong.
format	Theses and Dissertations
author	Zheng, Yuhong.
author_sort	Zheng, Yuhong.
title	Power optimization in data path allocation for high-level synthesis
title_short	Power optimization in data path allocation for high-level synthesis
title_full	Power optimization in data path allocation for high-level synthesis
title_fullStr	Power optimization in data path allocation for high-level synthesis
title_full_unstemmed	Power optimization in data path allocation for high-level synthesis
title_sort	power optimization in data path allocation for high-level synthesis
publishDate	2008
url	http://hdl.handle.net/10356/4049
_version_	1772826883602251776

Power optimization in data path allocation for high-level synthesis

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