Power optimization in data path allocation for high-level synthesis

• المؤلف الرئيسي: Zheng, Yuhong.
• مؤلفون آخرون: Jong, Ching Chuen
• التنسيق: Theses and Dissertations
• منشور في: 2008
• الموضوعات: DRNTU::Engineering::Electrical and electronic engineering::Power electronics
• الوصول للمادة أونلاين: http://hdl.handle.net/10356/4049

This thesis addresses the problem of minimizing power consumption in the high-level synthesis of data-dominated CMOS circuits.