Novel transistor structures for future deep submicron MOS applications

• Main Author: Theng, Ah Leong
• Other Authors: Goh Wang Ling
• Format: Theses and Dissertations
• Language: English
• Published: 2010
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: https://hdl.handle.net/10356/41403
• Institution: Nanyang Technological University

Bulk silicon CMOS processing is reaching the limits in device scaling and fabrication. Silicon-an-Insulator (Sal) technology provides an alternative. It not only allows better scalability but also a solution to low power and high performance applications for next generation CMOS devices. Fully depleted SOI transistors have emerged as one of the leading candidate for CMOS scaling. The possibility of using the back gate has sparked research activities in the field of novel non-classical SOI devices. In recent years, non-classical sal devices such as double, triple and quadruple multi-gate MOSFET have attracted vast interests in various research bodies and researchers.