Investigation of design techniques to reduce glitches for low power

This dissertation proposes and evaluates several glitch reduction techniques in the design of low power static CMOS circuits.

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Bibliographic Details
Main Author:	Foo, Chee Yin.
Other Authors:	Jong, Ching Chuen
Format:	Theses and Dissertations
Published:	2008
Subjects:	DRNTU::Engineering::Electrical and electronic engineering::Power electronics
Online Access:	http://hdl.handle.net/10356/4251
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Institution:	Nanyang Technological University

Description
Summary:	This dissertation proposes and evaluates several glitch reduction techniques in the design of low power static CMOS circuits.

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