Investigation of design techniques to reduce glitches for low power

This dissertation proposes and evaluates several glitch reduction techniques in the design of low power static CMOS circuits.

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Bibliographic Details
Main Author:	Foo, Chee Yin.
Other Authors:	Jong, Ching Chuen
Format:	Theses and Dissertations
Published:	2008
Subjects:	DRNTU::Engineering::Electrical and electronic engineering::Power electronics
Online Access:	http://hdl.handle.net/10356/4251
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Institution:	Nanyang Technological University

id	sg-ntu-dr.10356-4251
record_format	dspace
spelling	sg-ntu-dr.10356-42512023-07-04T15:15:04Z Investigation of design techniques to reduce glitches for low power Foo, Chee Yin. Jong, Ching Chuen School of Electrical and Electronic Engineering Liu, Po-Ching DRNTU::Engineering::Electrical and electronic engineering::Power electronics This dissertation proposes and evaluates several glitch reduction techniques in the design of low power static CMOS circuits. Master of Science (Integrated Circuit Design) 2008-09-17T09:47:43Z 2008-09-17T09:47:43Z 2003 2003 Thesis http://hdl.handle.net/10356/4251 Nanyang Technological University application/pdf
institution	Nanyang Technological University
building	NTU Library
continent	Asia
country	Singapore Singapore
content_provider	NTU Library
collection	DR-NTU
topic	DRNTU::Engineering::Electrical and electronic engineering::Power electronics
spellingShingle	DRNTU::Engineering::Electrical and electronic engineering::Power electronics Foo, Chee Yin. Investigation of design techniques to reduce glitches for low power
description	This dissertation proposes and evaluates several glitch reduction techniques in the design of low power static CMOS circuits.
author2	Jong, Ching Chuen
author_facet	Jong, Ching Chuen Foo, Chee Yin.
format	Theses and Dissertations
author	Foo, Chee Yin.
author_sort	Foo, Chee Yin.
title	Investigation of design techniques to reduce glitches for low power
title_short	Investigation of design techniques to reduce glitches for low power
title_full	Investigation of design techniques to reduce glitches for low power
title_fullStr	Investigation of design techniques to reduce glitches for low power
title_full_unstemmed	Investigation of design techniques to reduce glitches for low power
title_sort	investigation of design techniques to reduce glitches for low power
publishDate	2008
url	http://hdl.handle.net/10356/4251
_version_	1772826082715631616

Investigation of design techniques to reduce glitches for low power

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