Design and implementation of formal verification methodology using Boolean satisfiability

• 主要作者: Phone, Thet Khaing.
• 其他作者: Gwee Bah Hwee
• 格式: Final Year Project
• 語言: English
• 出版: 2011
• 主題: DRNTU::Engineering::Electrical and electronic engineering::Electronic systems
• 在線閱讀: http://hdl.handle.net/10356/42896

Functional verification is an important phase in the design flow of digital circuits as it is used to verify a design when changes occur. It ensures that the functionality of the original design is not affected by the changes. Logic simulation is a widely used technique for the verification of a des...