Design and implementation of formal verification methodology using Boolean satisfiability

Functional verification is an important phase in the design flow of digital circuits as it is used to verify a design when changes occur. It ensures that the functionality of the original design is not affected by the changes. Logic simulation is a widely used technique for the verification of a des...

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主要作者: Phone, Thet Khaing.
其他作者: Gwee Bah Hwee
格式: Final Year Project
語言:English
出版: 2011
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在線閱讀:http://hdl.handle.net/10356/42896
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