Design and implementation of formal verification methodology using Boolean satisfiability

• Main Author: Phone, Thet Khaing.
• Other Authors: Gwee Bah Hwee
• Format: Final Year Project
• Language: English
• Published: 2011
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic systems
• Online Access: http://hdl.handle.net/10356/42896
• Institution: Nanyang Technological University

Functional verification is an important phase in the design flow of digital circuits as it is used to verify a design when changes occur. It ensures that the functionality of the original design is not affected by the changes. Logic simulation is a widely used technique for the verification of a des...