De-embedding techniques for characterizing high frequency noise in nanometre CMOS devices

• Main Author: Loo, Xi Sung.
• Other Authors: Yeo Kiat Seng
• Format: Theses and Dissertations
• Language: English
• Published: 2012
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: http://hdl.handle.net/10356/49986
• Institution: Nanyang Technological University

Aggressive scaling of CMOS devices over the past decades has enabled System-on-Chip (SoC) solution which permits full integration of digital circuits with analog and RF functions in one chip at low cost. However, the growing complexity of radio frequency integrated circuits requires accurate characterization of CMOS device for successful modelling and IC design. High frequency noise measurement system has been used extensively for on-wafer noise characterization of CMOS devices. The device test fixture which consists of bond pads and interconnects provides essential connection interface between embedded transistor and measurement probes. However, undesired parasitic effects of test fixture left un-removed after calibration can significantly affect noise measurement of transistor device. Therefore, additional data processing steps, known as noise de-embedding is required to remove the impact of test structure parasitic effects from raw noise measurement data. Complex interaction of fixture parasitic at high frequency and dominance of fixture parasitic as device scaled down have imposed extreme challenges to noise de-embedding. Nevertheless, the development of a robust noise de-embedding technique is inevitable as the NFmin of CMOS device continues to decrease along the scaling trend and approach the uncertainty limit of measurement instrument. This research aims at developing an accurate noise de-embedding technique that can effectively extract noise parameters of CMOS devices of varying geometries and sizes at GHz range frequencies. Three de-embedding methods have been proposed for the purpose mentioned. The first de-embedding method is developed based on the hybrid two-port model. It is designed to remove the parasitic effects of transistor fixture for up to metal fingers while taking into consideration of contact resistance and its asymmetrical effects. The second method addresses the distributed effects of metal interconnects and forward coupling effects concurrently. It is based on a new cascade-parallel noise de-embedding methodology, which is useful for characterization of passive CMOS device as it offers de-embedding for up to the boundary of metal interconnects. The third de-embedding technique reveals the possible extension of previous cascade de-embedding approach for up to metal fingers. All these noise de-embedding methods have been verified on 130nm CMOS devices for possible application at millimeter-wave frequencies. Specifically, both the first and the last noise de-embedding methods have been shown to be scalable and accurate up to 80 GHz despite less silicon consumption by the afore-mentioned methods. The results reveal the importance of accounting for the parasitic effect of metal fingers for transistor characterization. Meanwhile, the second noise de-embedding method has been shown to be more accurate than existing cascade de-embedding approaches. The proposed de-embedding techniques discussed are also applicable to III-V compound transistor. Future noise de-embedding study could be extended for characterization of non-linear device.