Advanced wafer bonding for substrate engineering and 3D IC integration

• Main Author: Chong, Gang Yih
• Other Authors: Tan Chuan Seng
• Format: Theses and Dissertations
• Language: English
• Published: 2014
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Microelectronics
• Online Access: http://hdl.handle.net/10356/60478
• Institution: Nanyang Technological University

Three dimensional integrated circuits (3D ICs) in the form of several interconnected device layers which are stacked vertically offer a few advantages including improved device performance, form factor and heterogeneous integration. This thesis work is to develop an enabling process technology based on direct wafer fusion bonding at low temperature (< 400 Deg C). As compared to the conventional silicon oxide fusion bonding, a new modified Plasma Enhanced TetraEthyl OrthoSilicate (PETEOS) silicon oxide fusion bonding is developed and introduced by capping the PETEOS with high-k dielectric material. This comes with the benefit of the improvement of the bond strength without the sacrificial of the electrical performances. A seamless bonding interface is also observed from the cross-sectional TEM image. Fundamental studies of low-k to low-k dielectric fusion bonding are carried out with the advantages on the bond strength enhancement and further reduction of the overall dielectric capacitance to improve the electrical performance in comparison to the conventional silicon oxide fusion bonding. After careful TEM observations, this low-k to low-k dielectric fusion bonding shows a bonding interface with no interfacial voids. Other than the dielectric fusion bonding, metal fusion bonding is explored and developed. Titanium nitride (TiN) fusion bonding is attempted and a significant bond strength improvement coupled with the formation of the void-free bonding interface is demonstrated with this type of bonding. In addition, TiN fusion bonding creates a vertical electrical conduction path that is suitable to be employed in the via-middle integration scheme of 3D ICs application. Copper (Cu) is prevalently used as the metal material candidate in the semiconductor industry. Therefore, Cu to Cu fusion bonding is investigated. However, owing to the rapid oxidation of Cu in the ambient and the formation of interfacial voids, another new modified Cu fusion bonding method is described. Similar in concept to the previous modified PETEOS silicon oxide fusion bonding with the insertion of high-k dielectric material on top of the PETEOS silicon oxide, TiN as the metallic conductive material is inserted on top of the Cu before the fusion bonding takes place. This modified Cu fusion bonding capped with TiN demonstrates no apparent formation of interfacial microvoids at the bonding interface. In addition, the electrical conduction characteristic is not jeopardized with the insertion of TiN as the inter-metal layer. Thermal characteristic for high-k (Al2O3) and TiN as the bonding interface materials with reference to PETEOS silicon oxide are also investigated for the application that requires a better thermal dissipation. The experimental results show that Al2O3 and TiN are the suitable candidates as effective heat dissipators.