Atomistic simulation study of high-κ oxide defects for understanding gate stack and RRAM reliability

High-κ Oxide Defects in the MOSFET gate stack and RRAM cell severely impact the device reliability. In this work, we conducted first-principles modeling and simulation to investigate BTI performance in the SiON, HfO2 and La doped HfO2 MOSFET gate stacks. The properties of VO, Oi and VO-Oi defect pai...

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Main Author: Gu, Chenjie
Other Authors: Ang Diing Shenp
Format: Theses and Dissertations
Language:English
Published: 2015
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Online Access:https://hdl.handle.net/10356/62224
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-622242023-07-04T16:31:00Z Atomistic simulation study of high-κ oxide defects for understanding gate stack and RRAM reliability Gu, Chenjie Ang Diing Shenp School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Microelectronics High-κ Oxide Defects in the MOSFET gate stack and RRAM cell severely impact the device reliability. In this work, we conducted first-principles modeling and simulation to investigate BTI performance in the SiON, HfO2 and La doped HfO2 MOSFET gate stacks. The properties of VO, Oi and VO-Oi defect pair are studied, and unique behaviors of these defects which attribute to the BTI degradation in the aforementioned device gate stack are presented. Thereafter, the understanding of the defects in the hafnium oxide is extended to the RRAM study. We exhibit the key role of the forming step in generating the switchable conductive filament, and meanwhile an alternative method by using of Pt as the bottom electrode to mediate the conductive filament generation is introduced. DOCTOR OF PHILOSOPHY (EEE) 2015-03-09T07:26:22Z 2015-03-09T07:26:22Z 2015 2015 Thesis Gu, C. (2015). Atomistic simulation study of high-κ oxide defects for understanding gate stack and RRAM reliability. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/62224 10.32657/10356/62224 en 238 p. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic DRNTU::Engineering::Electrical and electronic engineering::Microelectronics
spellingShingle DRNTU::Engineering::Electrical and electronic engineering::Microelectronics
Gu, Chenjie
Atomistic simulation study of high-κ oxide defects for understanding gate stack and RRAM reliability
description High-κ Oxide Defects in the MOSFET gate stack and RRAM cell severely impact the device reliability. In this work, we conducted first-principles modeling and simulation to investigate BTI performance in the SiON, HfO2 and La doped HfO2 MOSFET gate stacks. The properties of VO, Oi and VO-Oi defect pair are studied, and unique behaviors of these defects which attribute to the BTI degradation in the aforementioned device gate stack are presented. Thereafter, the understanding of the defects in the hafnium oxide is extended to the RRAM study. We exhibit the key role of the forming step in generating the switchable conductive filament, and meanwhile an alternative method by using of Pt as the bottom electrode to mediate the conductive filament generation is introduced.
author2 Ang Diing Shenp
author_facet Ang Diing Shenp
Gu, Chenjie
format Theses and Dissertations
author Gu, Chenjie
author_sort Gu, Chenjie
title Atomistic simulation study of high-κ oxide defects for understanding gate stack and RRAM reliability
title_short Atomistic simulation study of high-κ oxide defects for understanding gate stack and RRAM reliability
title_full Atomistic simulation study of high-κ oxide defects for understanding gate stack and RRAM reliability
title_fullStr Atomistic simulation study of high-κ oxide defects for understanding gate stack and RRAM reliability
title_full_unstemmed Atomistic simulation study of high-κ oxide defects for understanding gate stack and RRAM reliability
title_sort atomistic simulation study of high-κ oxide defects for understanding gate stack and rram reliability
publishDate 2015
url https://hdl.handle.net/10356/62224
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