Networks on chip for FPGAs

• Main Author: Agarwal, Shubham
• Other Authors: Nachiket Kapre
• Format: Final Year Project
• Language: English
• Published: 2016
• Subjects: DRNTU::Engineering
• Online Access: http://hdl.handle.net/10356/66694
• Institution: Nanyang Technological University

Reducing worst case routing latencies while delivering high throughput and low energy are key design concerns in the engineering of overlay packet-switched NoCs for FPGA fabrics. Deflection Torus (Hoplite), an efficient, remarkably lightweight, fast FPGA overlay NoC that is designed to be small and compact by (1) eliminating input buffers, and (2) reducing the cost of switch crossbar (by using unidirectional torus instead of bidirectional) that have traditionally limited speeds and imposed heavy resource costs in conventional FPGA overlay NOCs. Though it delivers high sustained bandwidths for various workloads and traffic patterns, it suffers from significantly higher worst case routing latencies due to deflections, particularly at large system sizes (where the deflection cost/penalty is high), when compared to classic buffered NoCs. To tackle this, we design Hierarchical Deflection Torus that (1) targets worst case latencies in deflection torus NoCs by separating deflections into two levels of the NoC, (2) delivers an FPGA-friendly design for deadlock freedom by providing physical escape channels in the lower levels. For instance with the 16x16 NoC, we reduce worst case deflection costs by 1.5–10x while simultaneously improving sustained rates by 1.5–2x and lowering energy requirements by 1.5–2x for a range of statistically-generated traffic patterns.