Networks on chip for FPGAs
Reducing worst case routing latencies while delivering high throughput and low energy are key design concerns in the engineering of overlay packet-switched NoCs for FPGA fabrics. Deflection Torus (Hoplite), an efficient, remarkably lightweight, fast FPGA overlay NoC that is designed to be small and...
Saved in:
主要作者: | |
---|---|
其他作者: | |
格式: | Final Year Project |
語言: | English |
出版: |
2016
|
主題: | |
在線閱讀: | http://hdl.handle.net/10356/66694 |
標簽: |
添加標簽
沒有標簽, 成為第一個標記此記錄!
|
機構: | Nanyang Technological University |
語言: | English |