Ultra low power asynchronous-logic quasi-delay-insensitive circuit design

• المؤلف الرئيسي: Ho, Weng Geng
• مؤلفون آخرون: School of Electrical and Electronic Engineering
• التنسيق: Theses and Dissertations
• اللغة: English
• منشور في: 2016
• الموضوعات: DRNTU::Engineering
• الوصول للمادة أونلاين: http://hdl.handle.net/10356/68838
• المؤسسة: Nanyang Technological University

This thesis pertains to the investigation of low power, high robustness and yet speed-efficient digital electronics for portable/mobile/secured applications. We adopt the esoteric asynchronous-logic (async) vis-à-vis the conventional synchronous-logic (sync); more specifically, the async quasi-delay...