Ultra low power asynchronous-logic quasi-delay-insensitive circuit design
This thesis pertains to the investigation of low power, high robustness and yet speed-efficient digital electronics for portable/mobile/secured applications. We adopt the esoteric asynchronous-logic (async) vis-à-vis the conventional synchronous-logic (sync); more specifically, the async quasi-delay...
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| 格式: | Theses and Dissertations |
| 語言: | English |
| 出版: |
2016
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| 主題: | |
| 在線閱讀: | http://hdl.handle.net/10356/68838 |
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