Mechanical characterization and analysis of thin-film stacked structures for microelectronic assembly

The trend towards cost reduction, improved reliability, and increased functionality and performance in the power electronic product leads to a continuous implementation of new designs, materials, processes, and evaluation methodologies for chip- and package-level interconnections. Due to such trend,...

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Main Author: Yeo, Swain Hong
Other Authors: Zhou Kun
Format: Theses and Dissertations
Language:English
Published: 2017
Subjects:
Online Access:http://hdl.handle.net/10356/72665
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Institution: Nanyang Technological University
Language: English
id sg-ntu-dr.10356-72665
record_format dspace
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic DRNTU::Engineering::Materials::Microelectronics and semiconductor materials::Thin films
DRNTU::Engineering::Materials::Material testing and characterization
DRNTU::Engineering::Electrical and electronic engineering::Electronic packaging
spellingShingle DRNTU::Engineering::Materials::Microelectronics and semiconductor materials::Thin films
DRNTU::Engineering::Materials::Material testing and characterization
DRNTU::Engineering::Electrical and electronic engineering::Electronic packaging
Yeo, Swain Hong
Mechanical characterization and analysis of thin-film stacked structures for microelectronic assembly
description The trend towards cost reduction, improved reliability, and increased functionality and performance in the power electronic product leads to a continuous implementation of new designs, materials, processes, and evaluation methodologies for chip- and package-level interconnections. Due to such trend, the shrinking of integrated circuit (IC) features has raised a serious concern about the robustness of the thin-film stacked structure in the bond pad of an IC chip, especially on the wafer probe testing and wire bonding process in the chip-to-package interconnection. Furthermore, copper (Cu) wires have started to replace gold (Au) wires in the wire interconnection due to their superb cost advantageous, and excellent thermal and electrical performances. However, this hard Cu material makes the wire bonding on the bond pad of an IC chip much more challenging, where excessive deformation and damage of sensitive structures underneath the bond pad could happen. Moreover, cracking normally occurs at a brittle hard dielectric layer underneath the top metallization pad, which is not visible and difficult to detect, and thus it is important to understand and predict the mechanical response of the thin-film stacked structure of the bond pad under the wire bonding process. Hence, this research aims to study the mechanical behaviors and damage mechanisms of the thin-film stacked structures under indentation loading through both experimental study and numerical simulation. Firstly, an indentation damage test method is established using a micro-mechanical tester integrated with an acoustic emission (AE) sensor for crack detection in the specimen during the indentation loading-unloading cycle. The bulk Si die is first employed to investigate the integration of the indentation testing with the AE sensing, where the AE signal response is examined upon the occurrence of the onset cracking at the critical force Fc or displacement dc. The effects of the coupling medium between the specimen and AE sensor, and the specimen indentation position on the AE signal response are systematically studied. Secondly, the indentation damage test is employed to evaluate the bulk Si die and different thin-film stacked systems consisting of a top metal layer (aluminium Al or copper-titanium CuTi) and intermediate dielectric (silicon dioxide SiO2 or silicon nitride Si3N4) layers on the Si substrate. During the indentation, the first AE event corresponds to the “pop-in” or plateau is observed in the F-d curve, which is mainly due to the brittle cracking in the dielectric layer or/and Si substrate. Different failure modes are observed for different dielectric layers used in the thin-film stacked system, independent of the top metal layer materials. Besides the first AE event, a second or more AE events are also detected during the unloading stage due to the elastic recovery of the specimen, which lead to further crack propagation and delamination within the thin-film layers. A finite element model is established to simulate the loading-unloading process of the indentation on the bulk Si and the thin-film stacked system. The stress analysis is performed and correlated to the cracking of the specimens subjected to the indentation test, in which the damage mechanisms are uncovered. Thirdly, the work of indentation damage and fracture on the specimen are investigated. An indentation energy-based approach is proposed to determine the work of indentation fracture Wf based on the difference in elastic strain recovery between a damaged and a non-damaged specimen from the same maximum force, where the unloading begins. Two different techniques are developed to estimate Wf, namely the elastic-to-total work ratio and the integration of the unloading F-d curve. The relationship of the calculated Wf and the measured EAE is analyzed and discussed. In summary, this PhD study contributes to the understanding of the deformation, damage and cracking behavior of the thin-film stacked system subjected to the indentation loading-unloading cycle. This is essential in the processes of the wafer probing and wire bonding on the bond pad of an IC device, where the damage-sensitive pad can be identified and handled with care. Furthermore, the methodology can be used to optimize the structural robustness of the bond pad design, or implement as a mechanical screening tool for wafer quality check, which provides guidance in achieving optimal design for manufacturing reliable and durable microelectronic devices.
author2 Zhou Kun
author_facet Zhou Kun
Yeo, Swain Hong
format Theses and Dissertations
author Yeo, Swain Hong
author_sort Yeo, Swain Hong
title Mechanical characterization and analysis of thin-film stacked structures for microelectronic assembly
title_short Mechanical characterization and analysis of thin-film stacked structures for microelectronic assembly
title_full Mechanical characterization and analysis of thin-film stacked structures for microelectronic assembly
title_fullStr Mechanical characterization and analysis of thin-film stacked structures for microelectronic assembly
title_full_unstemmed Mechanical characterization and analysis of thin-film stacked structures for microelectronic assembly
title_sort mechanical characterization and analysis of thin-film stacked structures for microelectronic assembly
publishDate 2017
url http://hdl.handle.net/10356/72665
_version_ 1761781823253250048
spelling sg-ntu-dr.10356-726652023-03-11T18:00:12Z Mechanical characterization and analysis of thin-film stacked structures for microelectronic assembly Yeo, Swain Hong Zhou Kun School of Mechanical and Aerospace Engineering DRNTU::Engineering::Materials::Microelectronics and semiconductor materials::Thin films DRNTU::Engineering::Materials::Material testing and characterization DRNTU::Engineering::Electrical and electronic engineering::Electronic packaging The trend towards cost reduction, improved reliability, and increased functionality and performance in the power electronic product leads to a continuous implementation of new designs, materials, processes, and evaluation methodologies for chip- and package-level interconnections. Due to such trend, the shrinking of integrated circuit (IC) features has raised a serious concern about the robustness of the thin-film stacked structure in the bond pad of an IC chip, especially on the wafer probe testing and wire bonding process in the chip-to-package interconnection. Furthermore, copper (Cu) wires have started to replace gold (Au) wires in the wire interconnection due to their superb cost advantageous, and excellent thermal and electrical performances. However, this hard Cu material makes the wire bonding on the bond pad of an IC chip much more challenging, where excessive deformation and damage of sensitive structures underneath the bond pad could happen. Moreover, cracking normally occurs at a brittle hard dielectric layer underneath the top metallization pad, which is not visible and difficult to detect, and thus it is important to understand and predict the mechanical response of the thin-film stacked structure of the bond pad under the wire bonding process. Hence, this research aims to study the mechanical behaviors and damage mechanisms of the thin-film stacked structures under indentation loading through both experimental study and numerical simulation. Firstly, an indentation damage test method is established using a micro-mechanical tester integrated with an acoustic emission (AE) sensor for crack detection in the specimen during the indentation loading-unloading cycle. The bulk Si die is first employed to investigate the integration of the indentation testing with the AE sensing, where the AE signal response is examined upon the occurrence of the onset cracking at the critical force Fc or displacement dc. The effects of the coupling medium between the specimen and AE sensor, and the specimen indentation position on the AE signal response are systematically studied. Secondly, the indentation damage test is employed to evaluate the bulk Si die and different thin-film stacked systems consisting of a top metal layer (aluminium Al or copper-titanium CuTi) and intermediate dielectric (silicon dioxide SiO2 or silicon nitride Si3N4) layers on the Si substrate. During the indentation, the first AE event corresponds to the “pop-in” or plateau is observed in the F-d curve, which is mainly due to the brittle cracking in the dielectric layer or/and Si substrate. Different failure modes are observed for different dielectric layers used in the thin-film stacked system, independent of the top metal layer materials. Besides the first AE event, a second or more AE events are also detected during the unloading stage due to the elastic recovery of the specimen, which lead to further crack propagation and delamination within the thin-film layers. A finite element model is established to simulate the loading-unloading process of the indentation on the bulk Si and the thin-film stacked system. The stress analysis is performed and correlated to the cracking of the specimens subjected to the indentation test, in which the damage mechanisms are uncovered. Thirdly, the work of indentation damage and fracture on the specimen are investigated. An indentation energy-based approach is proposed to determine the work of indentation fracture Wf based on the difference in elastic strain recovery between a damaged and a non-damaged specimen from the same maximum force, where the unloading begins. Two different techniques are developed to estimate Wf, namely the elastic-to-total work ratio and the integration of the unloading F-d curve. The relationship of the calculated Wf and the measured EAE is analyzed and discussed. In summary, this PhD study contributes to the understanding of the deformation, damage and cracking behavior of the thin-film stacked system subjected to the indentation loading-unloading cycle. This is essential in the processes of the wafer probing and wire bonding on the bond pad of an IC device, where the damage-sensitive pad can be identified and handled with care. Furthermore, the methodology can be used to optimize the structural robustness of the bond pad design, or implement as a mechanical screening tool for wafer quality check, which provides guidance in achieving optimal design for manufacturing reliable and durable microelectronic devices. Doctor of Philosophy (MAE) 2017-09-08T06:16:52Z 2017-09-08T06:16:52Z 2017 Thesis Yeo, S. H. (2017). Mechanical characterization and analysis of thin-film stacked structures for microelectronic assembly. Doctoral thesis, Nanyang Technological University, Singapore. http://hdl.handle.net/10356/72665 10.32657/10356/72665 en 142 p. application/pdf