UVM based constrained random automated register verification of interface IP subsystem

• Main Author: Shanmuga Sundaram Santhosh Raju
• Other Authors: Andreas Herkersdorf
• Format: Theses and Dissertations
• Language: English
• Published: 2018
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: http://hdl.handle.net/10356/76069
• Institution: Nanyang Technological University

Modern Integrated Circuit (IC) designing is a huge and error-prone task that could potentially cost a fortune to the company even because of a minute glitch. In order to minimize the risks associated with the design of an IC, paramount importance is given to Verification process, if not in par with Design. Verification of ICs involves verifying the design for its functional correctness and contains several methodologies that have evolved with time as the design got bigger and better. In recent times, the Verification methodologies have evolved for efficiency, time and cost saving reasons. In this work, Universal Verification Methodology (UVM), a state-of-the-art industry standard verification methodology is used for the functional verification of registers of the Device under Test (DUT). The central idea of the work is to build a unified testbench with multiple interface functionalities like Advanced eXtensible Interface (AXI) and Advanced High-Performance Bus (AHB), for example. Whichever DUT has the available bus functionalities can simply get integrated with the testbench and get its register contents verified. In future, the testbench can also be extended by adding multiple other interfaces like Wishbone. While implementing the verification environment, several third-party Verification Intellectual Properties (VIP) are used for interfacing the DUT and developing the UVM based testbench. These VIPs play a major role in the proper working of the testbench.