UVM based constrained random automated register verification of interface IP subsystem

Modern Integrated Circuit (IC) designing is a huge and error-prone task that could potentially cost a fortune to the company even because of a minute glitch. In order to minimize the risks associated with the design of an IC, paramount importance is given to Verification process, if not in par with...

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Bibliographic Details
Main Author: Shanmuga Sundaram Santhosh Raju
Other Authors: Andreas Herkersdorf
Format: Theses and Dissertations
Language:English
Published: 2018
Subjects:
Online Access:http://hdl.handle.net/10356/76069
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Institution: Nanyang Technological University
Language: English
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