UVM based constrained random automated register verification of interface IP subsystem

• Main Author: Shanmuga Sundaram Santhosh Raju
• Other Authors: Andreas Herkersdorf
• Format: Theses and Dissertations
• Language: English
• Published: 2018
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: http://hdl.handle.net/10356/76069
• Institution: Nanyang Technological University

Modern Integrated Circuit (IC) designing is a huge and error-prone task that could potentially cost a fortune to the company even because of a minute glitch. In order to minimize the risks associated with the design of an IC, paramount importance is given to Verification process, if not in par with...