UVM based constrained random automated register verification of interface IP subsystem

• المؤلف الرئيسي: Shanmuga Sundaram Santhosh Raju
• مؤلفون آخرون: Andreas Herkersdorf
• التنسيق: Theses and Dissertations
• اللغة: English
• منشور في: 2018
• الموضوعات: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• الوصول للمادة أونلاين: http://hdl.handle.net/10356/76069

Modern Integrated Circuit (IC) designing is a huge and error-prone task that could potentially cost a fortune to the company even because of a minute glitch. In order to minimize the risks associated with the design of an IC, paramount importance is given to Verification process, if not in par with...