UVM based constrained random automated register verification of interface IP subsystem

• 主要作者: Shanmuga Sundaram Santhosh Raju
• 其他作者: Andreas Herkersdorf
• 格式: Theses and Dissertations
• 語言: English
• 出版: 2018
• 主題: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• 在線閱讀: http://hdl.handle.net/10356/76069
• 機構: Nanyang Technological University

Modern Integrated Circuit (IC) designing is a huge and error-prone task that could potentially cost a fortune to the company even because of a minute glitch. In order to minimize the risks associated with the design of an IC, paramount importance is given to Verification process, if not in par with...