Setup and implementation of hierarchical scan insertion using the core wrapping technique

• المؤلف الرئيسي: Saurabh, Maru
• مؤلفون آخرون: Gwee Bah Hwee
• التنسيق: Theses and Dissertations
• اللغة: English
• منشور في: 2018
• الموضوعات: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• الوصول للمادة أونلاين: http://hdl.handle.net/10356/76078

The rapid shrinking of the technology node from deep submicron levels to 90nm and below has allowed the complexity of the designs to increase without significantly increasing the chip size. Large designs are now posing many challenges to all design disciplines including design-for-test (DFT). For a...