Setup and implementation of hierarchical scan insertion using the core wrapping technique

• 主要作者: Saurabh, Maru
• 其他作者: Gwee Bah Hwee
• 格式: Theses and Dissertations
• 語言: English
• 出版: 2018
• 主題: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• 在線閱讀: http://hdl.handle.net/10356/76078
• 機構: Nanyang Technological University

The rapid shrinking of the technology node from deep submicron levels to 90nm and below has allowed the complexity of the designs to increase without significantly increasing the chip size. Large designs are now posing many challenges to all design disciplines including design-for-test (DFT). For a...