SPICE2: Spatial Processors Interconnected for Concurrent Execution for Accelerating the SPICE Circuit Simulator Using an FPGA

SPICE2: Spatial Processors Interconnected for Concurrent Execution for Accelerating the SPICE Circuit Simulator Using an FPGA

Spatial processing of sparse, irregular, double-precision floating-point computation using a single field-programmable gate array (FPGA) enables up to an order of magnitude speedup (mean 2.8× speedup) over a conventional microprocessor for the SPICE circuit simulator. We develop a parallel, FPGA-bas...

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Main Authors: Kapre, Nachiket, DeHon, André
其他作者: School of Computer Engineering
格式: Article
語言:English
出版: 2015
主題:
Reconfigurable logic
Simulation
Parallelism
在線閱讀:https://hdl.handle.net/10356/81197
http://hdl.handle.net/10220/39201
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機構: Nanyang Technological University
語言: English

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https://hdl.handle.net/10356/81197
http://hdl.handle.net/10220/39201

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