Timing Fault Detection in FPGA-Based Circuits

• Main Authors: Stott, Edward, Levine, Joshua M., Kapre, Nachiket, Cheung, Peter Y. K.
• 其他作者: School of Computer Engineering
• 格式: Conference or Workshop Item
• 語言: English
• 出版: 2015
• 主題: Computer Science and Engineering
• 在線閱讀: https://hdl.handle.net/10356/81248; http://hdl.handle.net/10220/39203
• 機構: Nanyang Technological University

The operation of FPGA systems, like most VLSI technology, is traditionally governed by static timing analysis, whereby safety margins for operating and manufacturing uncertainty are factored in at design-time. If we operate FPGA designs beyond these conservative margins we can obtain substantial ene...