Timing Fault Detection in FPGA-Based Circuits

• المؤلفون الرئيسيون: Stott, Edward, Levine, Joshua M., Kapre, Nachiket, Cheung, Peter Y. K.
• مؤلفون آخرون: School of Computer Engineering
• التنسيق: Conference or Workshop Item
• اللغة: English
• منشور في: 2015
• الموضوعات: Computer Science and Engineering
• الوصول للمادة أونلاين: https://hdl.handle.net/10356/81248; http://hdl.handle.net/10220/39203

The operation of FPGA systems, like most VLSI technology, is traditionally governed by static timing analysis, whereby safety margins for operating and manufacturing uncertainty are factored in at design-time. If we operate FPGA designs beyond these conservative margins we can obtain substantial energy and performance improvements. However, doing this carelessly would cause unacceptable impacts to reliability, lifespan and yield - issues which are growing more severe with continuing process scaling. Fortunately, the flexibility of FPGA architecture allows us to monitor and control reliability problems with a variety of runtime instrumentation and adaptation techniques. In this paper we develop a system for detecting timing faults in arbitrary FPGA circuits based on Razor-like shadow register insertion. Through a combination of calibration, timing constraint and adaptation of the CAD flow, we deliver low-overhead, trustworthy fault detection for FPGA-based circuits.