Timing Fault Detection in FPGA-Based Circuits
The operation of FPGA systems, like most VLSI technology, is traditionally governed by static timing analysis, whereby safety margins for operating and manufacturing uncertainty are factored in at design-time. If we operate FPGA designs beyond these conservative margins we can obtain substantial ene...
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sg-ntu-dr.10356-812482020-05-28T07:19:24Z Timing Fault Detection in FPGA-Based Circuits Stott, Edward Levine, Joshua M. Kapre, Nachiket Cheung, Peter Y. K. School of Computer Engineering 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Computer Science and Engineering The operation of FPGA systems, like most VLSI technology, is traditionally governed by static timing analysis, whereby safety margins for operating and manufacturing uncertainty are factored in at design-time. If we operate FPGA designs beyond these conservative margins we can obtain substantial energy and performance improvements. However, doing this carelessly would cause unacceptable impacts to reliability, lifespan and yield - issues which are growing more severe with continuing process scaling. Fortunately, the flexibility of FPGA architecture allows us to monitor and control reliability problems with a variety of runtime instrumentation and adaptation techniques. In this paper we develop a system for detecting timing faults in arbitrary FPGA circuits based on Razor-like shadow register insertion. Through a combination of calibration, timing constraint and adaptation of the CAD flow, we deliver low-overhead, trustworthy fault detection for FPGA-based circuits. Accepted version 2015-12-22T09:06:30Z 2019-12-06T14:26:29Z 2015-12-22T09:06:30Z 2019-12-06T14:26:29Z 2014 Conference Paper Stott, E., Levine, J. M., Cheung, P. Y. K., & Kapre, N. (2014). Timing Fault Detection in FPGA-Based Circuits. 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines, 96-99. https://hdl.handle.net/10356/81248 http://hdl.handle.net/10220/39203 10.1109/FCCM.2014.32 en © 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/FCCM.2014.32]. 4 p. application/pdf |
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Computer Science and Engineering Stott, Edward Levine, Joshua M. Kapre, Nachiket Cheung, Peter Y. K. Timing Fault Detection in FPGA-Based Circuits |
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The operation of FPGA systems, like most VLSI technology, is traditionally governed by static timing analysis, whereby safety margins for operating and manufacturing uncertainty are factored in at design-time. If we operate FPGA designs beyond these conservative margins we can obtain substantial energy and performance improvements. However, doing this carelessly would cause unacceptable impacts to reliability, lifespan and yield - issues which are growing more severe with continuing process scaling. Fortunately, the flexibility of FPGA architecture allows us to monitor and control reliability problems with a variety of runtime instrumentation and adaptation techniques. In this paper we develop a system for detecting timing faults in arbitrary FPGA circuits based on Razor-like shadow register insertion. Through a combination of calibration, timing constraint and adaptation of the CAD flow, we deliver low-overhead, trustworthy fault detection for FPGA-based circuits. |
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School of Computer Engineering |
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School of Computer Engineering Stott, Edward Levine, Joshua M. Kapre, Nachiket Cheung, Peter Y. K. |
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Conference or Workshop Item |
author |
Stott, Edward Levine, Joshua M. Kapre, Nachiket Cheung, Peter Y. K. |
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Stott, Edward |
title |
Timing Fault Detection in FPGA-Based Circuits |
title_short |
Timing Fault Detection in FPGA-Based Circuits |
title_full |
Timing Fault Detection in FPGA-Based Circuits |
title_fullStr |
Timing Fault Detection in FPGA-Based Circuits |
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Timing Fault Detection in FPGA-Based Circuits |
title_sort |
timing fault detection in fpga-based circuits |
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2015 |
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https://hdl.handle.net/10356/81248 http://hdl.handle.net/10220/39203 |
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