Timing Fault Detection in FPGA-Based Circuits

• Main Authors: Stott, Edward, Levine, Joshua M., Kapre, Nachiket, Cheung, Peter Y. K.
• Other Authors: School of Computer Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2015
• Subjects: Computer Science and Engineering
• Online Access: https://hdl.handle.net/10356/81248; http://hdl.handle.net/10220/39203
• Institution: Nanyang Technological University

The operation of FPGA systems, like most VLSI technology, is traditionally governed by static timing analysis, whereby safety margins for operating and manufacturing uncertainty are factored in at design-time. If we operate FPGA designs beyond these conservative margins we can obtain substantial ene...