Integration of GaAs, GaN, and Si-CMOS on a common 200 mm Si substrate through multilayer transfer process

Integration of GaAs, GaN, and Si-CMOS on a common 200 mm Si substrate through multilayer transfer process

The integration of III–V semiconductors (e.g., GaAs and GaN) and silicon-on-insulator (SOI)-CMOS on a 200 mm Si substrate is demonstrated. The SOI-CMOS donor wafer is temporarily bonded on a Si handle wafer and thinned down. A second GaAs/Ge/Si substrate is then bonded to the SOI-CMOS-containing han...

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Bibliographic Details
Main Authors: Lee, Kwang Hong, Bao, Shuyu, Zhang, Li, Kohen, David, Fitzgerald, Eugene, Tan, Chuan Seng
Other Authors: School of Electrical and Electronic Engineering
Format: Article
Language:English
Published: 2017
Subjects:
CMOS integrated circuits
Gallium arsenide
Online Access:https://hdl.handle.net/10356/82889
http://hdl.handle.net/10220/42320
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Institution: Nanyang Technological University
Language: English
Description
Summary:The integration of III–V semiconductors (e.g., GaAs and GaN) and silicon-on-insulator (SOI)-CMOS on a 200 mm Si substrate is demonstrated. The SOI-CMOS donor wafer is temporarily bonded on a Si handle wafer and thinned down. A second GaAs/Ge/Si substrate is then bonded to the SOI-CMOS-containing handle wafer. After that, the Si from the GaAs/Ge/Si substrate is removed. The GaN/Si substrate is then bonded to the SOI–GaAs/Ge-containing handle wafer. Finally, the handle wafer is released to realize the SOI–GaAs/Ge/GaN/Si hybrid structure on a Si substrate. By this method, the functionalities of the materials used can be combined on a single Si platform.

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