Integration of GaAs, GaN, and Si-CMOS on a common 200 mm Si substrate through multilayer transfer process

Integration of GaAs, GaN, and Si-CMOS on a common 200 mm Si substrate through multilayer transfer process

The integration of III–V semiconductors (e.g., GaAs and GaN) and silicon-on-insulator (SOI)-CMOS on a 200 mm Si substrate is demonstrated. The SOI-CMOS donor wafer is temporarily bonded on a Si handle wafer and thinned down. A second GaAs/Ge/Si substrate is then bonded to the SOI-CMOS-containing han...

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Main Authors: Lee, Kwang Hong, Bao, Shuyu, Zhang, Li, Kohen, David, Fitzgerald, Eugene, Tan, Chuan Seng
Other Authors: School of Electrical and Electronic Engineering
Format: Article
Language:English
Published: 2017
Subjects:
CMOS integrated circuits
Gallium arsenide
Online Access:https://hdl.handle.net/10356/82889
http://hdl.handle.net/10220/42320
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-828892020-03-07T13:57:24Z Integration of GaAs, GaN, and Si-CMOS on a common 200 mm Si substrate through multilayer transfer process Lee, Kwang Hong Bao, Shuyu Zhang, Li Kohen, David Fitzgerald, Eugene Tan, Chuan Seng School of Electrical and Electronic Engineering CMOS integrated circuits Gallium arsenide The integration of III–V semiconductors (e.g., GaAs and GaN) and silicon-on-insulator (SOI)-CMOS on a 200 mm Si substrate is demonstrated. The SOI-CMOS donor wafer is temporarily bonded on a Si handle wafer and thinned down. A second GaAs/Ge/Si substrate is then bonded to the SOI-CMOS-containing handle wafer. After that, the Si from the GaAs/Ge/Si substrate is removed. The GaN/Si substrate is then bonded to the SOI–GaAs/Ge-containing handle wafer. Finally, the handle wafer is released to realize the SOI–GaAs/Ge/GaN/Si hybrid structure on a Si substrate. By this method, the functionalities of the materials used can be combined on a single Si platform. NRF (Natl Research Foundation, S’pore) Accepted version 2017-05-03T07:42:23Z 2019-12-06T15:07:38Z 2017-05-03T07:42:23Z 2019-12-06T15:07:38Z 2016 Journal Article Lee, K. H., Bao, S., Zhang, L., Kohen, D., Fitzgerald, E., & Tan, C. S. (2016). Integration of GaAs, GaN, and Si-CMOS on a common 200 mm Si substrate through multilayer transfer process. Applied Physics Express, 9(8), 086501-. 1882-0778 https://hdl.handle.net/10356/82889 http://hdl.handle.net/10220/42320 10.7567/APEX.9.086501 en Applied Physics Express © 2016 The Japan Society of Applied Physics. This is the author created version of a work that has been peer reviewed and accepted for publication by Applied Physics Express, The Japan Society of Applied Physics. It incorporates referee’s comments but changes resulting from the publishing process, such as copyediting, structural formatting, may not be reflected in this document. The published version is available at: [http://dx.doi.org/10.7567/APEX.9.086501]. 14 p. application/pdf
institution Nanyang Technological University
building NTU Library
country Singapore
collection DR-NTU
language English
topic CMOS integrated circuits
Gallium arsenide
spellingShingle CMOS integrated circuits
Gallium arsenide
Lee, Kwang Hong
Bao, Shuyu
Zhang, Li
Kohen, David
Fitzgerald, Eugene
Tan, Chuan Seng
Integration of GaAs, GaN, and Si-CMOS on a common 200 mm Si substrate through multilayer transfer process
description The integration of III–V semiconductors (e.g., GaAs and GaN) and silicon-on-insulator (SOI)-CMOS on a 200 mm Si substrate is demonstrated. The SOI-CMOS donor wafer is temporarily bonded on a Si handle wafer and thinned down. A second GaAs/Ge/Si substrate is then bonded to the SOI-CMOS-containing handle wafer. After that, the Si from the GaAs/Ge/Si substrate is removed. The GaN/Si substrate is then bonded to the SOI–GaAs/Ge-containing handle wafer. Finally, the handle wafer is released to realize the SOI–GaAs/Ge/GaN/Si hybrid structure on a Si substrate. By this method, the functionalities of the materials used can be combined on a single Si platform.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Lee, Kwang Hong
Bao, Shuyu
Zhang, Li
Kohen, David
Fitzgerald, Eugene
Tan, Chuan Seng
format Article
author Lee, Kwang Hong
Bao, Shuyu
Zhang, Li
Kohen, David
Fitzgerald, Eugene
Tan, Chuan Seng
author_sort Lee, Kwang Hong
title Integration of GaAs, GaN, and Si-CMOS on a common 200 mm Si substrate through multilayer transfer process
title_short Integration of GaAs, GaN, and Si-CMOS on a common 200 mm Si substrate through multilayer transfer process
title_full Integration of GaAs, GaN, and Si-CMOS on a common 200 mm Si substrate through multilayer transfer process
title_fullStr Integration of GaAs, GaN, and Si-CMOS on a common 200 mm Si substrate through multilayer transfer process
title_full_unstemmed Integration of GaAs, GaN, and Si-CMOS on a common 200 mm Si substrate through multilayer transfer process
title_sort integration of gaas, gan, and si-cmos on a common 200 mm si substrate through multilayer transfer process
publishDate 2017
url https://hdl.handle.net/10356/82889
http://hdl.handle.net/10220/42320
_version_ 1681038339577217024

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