Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM

We propose a novel 15-T Transmission-gate-based Non-Imprinting High-speed Erase (TNIHE) SRAM cell with emphases on low area overhead and low stand-by power attributes for highly secured data storage applications. We benchmark our proposed 15-T TNIHE SRAM cell against the reported 22-T Non-Imprinting...

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Main Authors: Ho, Weng-Geng, Ne, Kyaw Zwa Lwin, Prashanth Srinivas, Nagarajan, Chong, Kwen-Siong, Kim, Tony Tae-Hyoung, Gwee, Bah Hwee
Other Authors: School of Electrical and Electronic Engineering
Format: Conference or Workshop Item
Language:English
Published: 2016
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Online Access:https://hdl.handle.net/10356/83999
http://hdl.handle.net/10220/41565
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-839992020-03-07T13:24:44Z Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM Ho, Weng-Geng Ne, Kyaw Zwa Lwin Prashanth Srinivas, Nagarajan Chong, Kwen-Siong Kim, Tony Tae-Hyoung Gwee, Bah Hwee School of Electrical and Electronic Engineering 2016 IEEE International Symposium on Circuits and Systems (ISCAS) Centre for Integrated Circuits and Systems transistors SRAM cells We propose a novel 15-T Transmission-gate-based Non-Imprinting High-speed Erase (TNIHE) SRAM cell with emphases on low area overhead and low stand-by power attributes for highly secured data storage applications. We benchmark our proposed 15-T TNIHE SRAM cell against the reported 22-T Non-Imprinting High-speed Erase (NIHE) SRAM cell, and demonstrated three key features of reducing 7 transistors. First, we adopt the transmission gates (as opposed the cross-couple inverters) in the slave circuitry, saving 4 transistors. Second, we eliminate a transistor which uses to reset the slave circuitry, hence saving 1 transistor. Third, we apply the global inverse transistors (as opposed to the local inverse transistors) in the read /write circuit for each SRAM cell, hence further reduce 2 more transistors. As a result, our proposed TNIHE SRAM cell @ 65nm CMOS features ~17% smaller layout area. We design a 1k-byte memory based on the proposed TNIHE SRAM cells. On the basis of simulations, we show that our 1k-byte SRAM memory features overall ~13% smaller area, and dissipates on average, ~30% lower stand-by power than the reported NIHE counterpart. Accepted version 2016-10-17T03:52:26Z 2019-12-06T15:36:11Z 2016-10-17T03:52:26Z 2019-12-06T15:36:11Z 2016 Conference Paper Ho, W.-G., Ne, K. Z. L., Prashanth Srinivas, N., Chong, K.-S., Kim, T. T.-H., & Gwee, B. H. (2016). Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM. 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 698-701. https://hdl.handle.net/10356/83999 http://hdl.handle.net/10220/41565 10.1109/ISCAS.2016.7527336 en © 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/ISCAS.2016.7527336]. 4 p. application/pdf
institution Nanyang Technological University
building NTU Library
country Singapore
collection DR-NTU
language English
topic transistors
SRAM cells
spellingShingle transistors
SRAM cells
Ho, Weng-Geng
Ne, Kyaw Zwa Lwin
Prashanth Srinivas, Nagarajan
Chong, Kwen-Siong
Kim, Tony Tae-Hyoung
Gwee, Bah Hwee
Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM
description We propose a novel 15-T Transmission-gate-based Non-Imprinting High-speed Erase (TNIHE) SRAM cell with emphases on low area overhead and low stand-by power attributes for highly secured data storage applications. We benchmark our proposed 15-T TNIHE SRAM cell against the reported 22-T Non-Imprinting High-speed Erase (NIHE) SRAM cell, and demonstrated three key features of reducing 7 transistors. First, we adopt the transmission gates (as opposed the cross-couple inverters) in the slave circuitry, saving 4 transistors. Second, we eliminate a transistor which uses to reset the slave circuitry, hence saving 1 transistor. Third, we apply the global inverse transistors (as opposed to the local inverse transistors) in the read /write circuit for each SRAM cell, hence further reduce 2 more transistors. As a result, our proposed TNIHE SRAM cell @ 65nm CMOS features ~17% smaller layout area. We design a 1k-byte memory based on the proposed TNIHE SRAM cells. On the basis of simulations, we show that our 1k-byte SRAM memory features overall ~13% smaller area, and dissipates on average, ~30% lower stand-by power than the reported NIHE counterpart.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Ho, Weng-Geng
Ne, Kyaw Zwa Lwin
Prashanth Srinivas, Nagarajan
Chong, Kwen-Siong
Kim, Tony Tae-Hyoung
Gwee, Bah Hwee
format Conference or Workshop Item
author Ho, Weng-Geng
Ne, Kyaw Zwa Lwin
Prashanth Srinivas, Nagarajan
Chong, Kwen-Siong
Kim, Tony Tae-Hyoung
Gwee, Bah Hwee
author_sort Ho, Weng-Geng
title Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM
title_short Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM
title_full Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM
title_fullStr Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM
title_full_unstemmed Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM
title_sort area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (tnihe) sram
publishDate 2016
url https://hdl.handle.net/10356/83999
http://hdl.handle.net/10220/41565
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