Short-channel drain current model for asymmetric heavily / lightly doped DG MOSFETs

• Main Authors: Dutta, Pradipta, Syamal, Binit, Koley, Kalyan, Dutta, Arka, Sarkar, C. K.
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2018
• Subjects: Asymmetric Double Gate; Drain Current
• Online Access: https://hdl.handle.net/10356/89322; http://hdl.handle.net/10220/44866
• Institution: Nanyang Technological University

The paper presents a drain current model for double gate metal oxide semiconductor field effect transistors (DG MOSFETs) based on a new velocity saturation model that accounts for short-channel velocity saturation effect independently in the front and the back gate controlled channels under asymmetric front and back gate bias and oxide thickness. To determine the front and the back-channel velocity saturation, drain-induced barrier lowering is evaluated by effective gate voltages at the front and back gates obtained from surface potential at the threshold condition after considering symmetric and asymmetric front and back oxide thickness. The model also incorporates surface roughness scattering and ionized impurity scattering to estimate drain current for heavily / lightly doped channel for short-channel asymmetric DG MOSFET and a good agreement has been achieved with TCAD simulations, with a relative error of around 3–7%.