Electrical characterization of dielectrically isolated silicon substrates containing buried metallic layers

Dielectrically isolated substrates containing buried highly conducting WSi2 layers are characterized for the first time using MOS capacitors. The active silicon layer is approximately 3 µm thick with a buried WSi2 layer 120 mm thick adjacent to the isolation layer. The buried metal forms the back co...

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Main Authors:	Goh, Wang Ling, Montgomery, J. H., Raza, S. H., Gamble, H. S., Armstrong, B. M.
Other Authors:	School of Electrical and Electronic Engineering
Format:	Article
Language:	English
Published:	2009
Subjects:	DRNTU::Engineering::Electrical and electronic engineering
Online Access:	https://hdl.handle.net/10356/91578 http://hdl.handle.net/10220/6017
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Institution:	Nanyang Technological University
Language:	English

id	sg-ntu-dr.10356-91578
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spelling	sg-ntu-dr.10356-915782020-03-07T14:02:41Z Electrical characterization of dielectrically isolated silicon substrates containing buried metallic layers Goh, Wang Ling Montgomery, J. H. Raza, S. H. Gamble, H. S. Armstrong, B. M. School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering Dielectrically isolated substrates containing buried highly conducting WSi2 layers are characterized for the first time using MOS capacitors. The active silicon layer is approximately 3 µm thick with a buried WSi2 layer 120 mm thick adjacent to the isolation layer. The buried metal forms the back contact of the capacitor and excellent MOS characteristics are observed. Minority carrier lifetimes in excess of 200 µs were measured indicating the suitability of these substrates for use in device manufacture. Published version 2009-08-03T06:14:14Z 2019-12-06T18:08:14Z 2009-08-03T06:14:14Z 2019-12-06T18:08:14Z 1997 1997 Journal Article Goh, W. L., Montgomery, J. H., Raza, S. H., Gamble, H. S., & Armstrong, B. M. (1997). Electrical characterization of dielectrically isolated silicon substrates containing buried metallic layers. IEEE Electron Device Letters, 18(5), 232-234. 0741-3106 https://hdl.handle.net/10356/91578 http://hdl.handle.net/10220/6017 10.1109/55.568777 en IEEE electron device letters IEEE Electron Device Letters © 1997 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site. 3 p. application/pdf
institution	Nanyang Technological University
building	NTU Library
country	Singapore
collection	DR-NTU
language	English
topic	DRNTU::Engineering::Electrical and electronic engineering
spellingShingle	DRNTU::Engineering::Electrical and electronic engineering Goh, Wang Ling Montgomery, J. H. Raza, S. H. Gamble, H. S. Armstrong, B. M. Electrical characterization of dielectrically isolated silicon substrates containing buried metallic layers
description	Dielectrically isolated substrates containing buried highly conducting WSi2 layers are characterized for the first time using MOS capacitors. The active silicon layer is approximately 3 µm thick with a buried WSi2 layer 120 mm thick adjacent to the isolation layer. The buried metal forms the back contact of the capacitor and excellent MOS characteristics are observed. Minority carrier lifetimes in excess of 200 µs were measured indicating the suitability of these substrates for use in device manufacture.
author2	School of Electrical and Electronic Engineering
author_facet	School of Electrical and Electronic Engineering Goh, Wang Ling Montgomery, J. H. Raza, S. H. Gamble, H. S. Armstrong, B. M.
format	Article
author	Goh, Wang Ling Montgomery, J. H. Raza, S. H. Gamble, H. S. Armstrong, B. M.
author_sort	Goh, Wang Ling
title	Electrical characterization of dielectrically isolated silicon substrates containing buried metallic layers
title_short	Electrical characterization of dielectrically isolated silicon substrates containing buried metallic layers
title_full	Electrical characterization of dielectrically isolated silicon substrates containing buried metallic layers
title_fullStr	Electrical characterization of dielectrically isolated silicon substrates containing buried metallic layers
title_full_unstemmed	Electrical characterization of dielectrically isolated silicon substrates containing buried metallic layers
title_sort	electrical characterization of dielectrically isolated silicon substrates containing buried metallic layers
publishDate	2009
url	https://hdl.handle.net/10356/91578 http://hdl.handle.net/10220/6017
_version_	1681047213569998848

Electrical characterization of dielectrically isolated silicon substrates containing buried metallic layers

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