Si ion-induced instability in flatband voltage of Si+ -implanted gate oxides

• Main Authors: Chen, Q., Zhao, P., Tseng, Ampere A., Ng, Chi Yung, Chen, Tupei, Ding, Liang, Liu, Yang, Fung, Stevenson Hon Yuen
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2010
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic apparatus and materials
• Online Access: https://hdl.handle.net/10356/92134; http://hdl.handle.net/10220/6405
• Institution: Nanyang Technological University

Effect of the trapped Si ions in a 30-nm gate oxide implanted with Si+ at a very low energy (1.3 keV) on the flatband voltage after various thermal annealing has been examined. For the annealing at 700°C for 20 min, although only 0.1 per cent of the implanted Si ions remained, it can cause a flatband voltage shift of -21.3 V, and the flatband voltage shift reduces with time under a negative gate voltage showing neutralization of the trapped ions by the injected electrons from the gate. However, the annealing at 900°C for 20 min has reduced the number of the remaining ions to the lowest limit corresponding to a flatband voltage shift of -0.1 V, and the application of the negative voltage does not change the flatband voltage. A higher annealing temperature or a longer annealing time does not show further improvement, suggesting that the annealing at 900°C for 20 min is sufficient for eliminating the effect of the trapped ions.