Concurrent error detection in bit-serial normal basis multiplication over GF(2^m) using multiple parity prediction schemes

Concurrent error detection in bit-serial normal basis multiplication over GF(2^m) using multiple parity prediction schemes

New bit-serial architectures with concurrent error detection capability are presented to detect erroneous outputs in bit-serial normal basis multipliers over GF(2^m) using single and multiple-parity prediction schemes. It is shown that different types of normal basis multipliers could be realized by...

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Main Authors: Lee, Chiou Yng, Meher, Pramod Kumar, Patra, Jagdish Chandra
Other Authors: School of Computer Engineering
Format: Article
Language:English
Published: 2011
Subjects:
DRNTU::Engineering::Computer science and engineering::Computer systems organization::Computer-communication networks
Online Access:https://hdl.handle.net/10356/94346
http://hdl.handle.net/10220/7120
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-943462020-05-28T07:17:24Z Concurrent error detection in bit-serial normal basis multiplication over GF(2^m) using multiple parity prediction schemes Lee, Chiou Yng Meher, Pramod Kumar Patra, Jagdish Chandra School of Computer Engineering DRNTU::Engineering::Computer science and engineering::Computer systems organization::Computer-communication networks New bit-serial architectures with concurrent error detection capability are presented to detect erroneous outputs in bit-serial normal basis multipliers over GF(2^m) using single and multiple-parity prediction schemes. It is shown that different types of normal basis multipliers could be realized by similar architectures. The proposed architectures can detect errors with nearly 100% probability. Accepted version 2011-09-29T06:13:25Z 2019-12-06T18:54:36Z 2011-09-29T06:13:25Z 2019-12-06T18:54:36Z 2010 2010 Journal Article Lee, C. Y., Meher, P. K., & Patra, J. C. (2010). Concurrent Error Detection in Bit-Serial Normal Basis Multiplication Over GF (2^m) Using Multiple Parity Prediction Schemes. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18(8), 1234-1238. 1063-8210 https://hdl.handle.net/10356/94346 http://hdl.handle.net/10220/7120 10.1109/TVLSI.2009.2020593 141722 en IEEE transactions on very large scale integration (VLSI) systems © 2009 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [DOI: http://dx.doi.org/10.1109/TVLSI.2009.2020593]. 5 p. application/pdf
institution Nanyang Technological University
building NTU Library
country Singapore
collection DR-NTU
language English
topic DRNTU::Engineering::Computer science and engineering::Computer systems organization::Computer-communication networks
spellingShingle DRNTU::Engineering::Computer science and engineering::Computer systems organization::Computer-communication networks
Lee, Chiou Yng
Meher, Pramod Kumar
Patra, Jagdish Chandra
Concurrent error detection in bit-serial normal basis multiplication over GF(2^m) using multiple parity prediction schemes
description New bit-serial architectures with concurrent error detection capability are presented to detect erroneous outputs in bit-serial normal basis multipliers over GF(2^m) using single and multiple-parity prediction schemes. It is shown that different types of normal basis multipliers could be realized by similar architectures. The proposed architectures can detect errors with nearly 100% probability.
author2 School of Computer Engineering
author_facet School of Computer Engineering
Lee, Chiou Yng
Meher, Pramod Kumar
Patra, Jagdish Chandra
format Article
author Lee, Chiou Yng
Meher, Pramod Kumar
Patra, Jagdish Chandra
author_sort Lee, Chiou Yng
title Concurrent error detection in bit-serial normal basis multiplication over GF(2^m) using multiple parity prediction schemes
title_short Concurrent error detection in bit-serial normal basis multiplication over GF(2^m) using multiple parity prediction schemes
title_full Concurrent error detection in bit-serial normal basis multiplication over GF(2^m) using multiple parity prediction schemes
title_fullStr Concurrent error detection in bit-serial normal basis multiplication over GF(2^m) using multiple parity prediction schemes
title_full_unstemmed Concurrent error detection in bit-serial normal basis multiplication over GF(2^m) using multiple parity prediction schemes
title_sort concurrent error detection in bit-serial normal basis multiplication over gf(2^m) using multiple parity prediction schemes
publishDate 2011
url https://hdl.handle.net/10356/94346
http://hdl.handle.net/10220/7120
_version_ 1681058520680628224

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