Sensing margin enhancement techniques for ultra-low-voltage SRAMs utilizing a bitline-boosting current and equalized bitline leakage

• Main Authors: Do, Anh Tuan, Nguyen, Truc Quynh, Yeo, Kiat Seng, Kim, Tony Tae-Hyoung
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/95955; http://hdl.handle.net/10220/11361
• Institution: Nanyang Technological University

A small bitline sensing margin is one of the most challenging design obstacles for reliable ultra-low-voltage static random access memory (SRAM) implementation. This paper presents design techniques for bitline sensing margin enhancement using decoupled SRAMs. The proposed bitline-boosting current scheme improves the bitline sensing margin at a given bitline configuration. The bitline sensing margin can be further augmented by equalizing bitline leakage. Simulation using a 40-nm CMOS process shows that the proposed techniques achieve larger bitline sensing margin, wider operating temperature and supply range, and a larger number of cells per bitline.