Scalable linear array architectures for matrix inversion using Bi-z CORDIC
In this paper, VLSI array architectures for matrix inversion are studied. A new binary-coded z-path (Bi-z) CORDIC is developed and implemented to compute the operations required in the matrix inversion using the Givens rotation (GR) based QR decomposition. The Bi-z CORDIC allows both the GR vectorin...
Saved in:
Main Authors: | Luo, J. W., Jong, Ching Chuen |
---|---|
Other Authors: | School of Electrical and Electronic Engineering |
Format: | Article |
Language: | English |
Published: |
2013
|
Subjects: | |
Online Access: | https://hdl.handle.net/10356/98429 http://hdl.handle.net/10220/11150 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |
Language: | English |
Similar Items
-
Scalable and configurable array architectures for matrix computation
by: Luo, Jianwen
Published: (2008) -
Cordic BPSK demodulator
by: Alappat Vintu Jose
Published: (2010) -
A memory-efficient scalable architecture for lifting-based discrete wavelet transform
by: Hu, Yusong, et al.
Published: (2013) -
A unified architecture for flat CORDIC
by: Bimal Gisuthan.
Published: (2008) -
Fixed-point analysis and parameter selections of MSR-CORDIC with applications to FFT designs
by: Park, Sang Yoon, et al.
Published: (2013)