Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells

10.1109/TVLSI.2013.2239671

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Bibliographic Details
Main Authors:	Fong, Xuanyao, Kim, Yusung, Choday, Sri Harsha, Roy, Kaushik
Other Authors:	DEPT OF ELECTRICAL & COMPUTER ENGG
Format:	Article
Language:	English
Published:	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC 2019
Subjects:	Science & Technology Technology Computer Science, Hardware & Architecture Engineering, Electrical & Electronic Computer Science Engineering Bit-cell optimization failure mitigation magnetic tunneling junction (MTJ) spin-transfer torque magnetic RAM (STT-MRAM) MAGNETIC TUNNEL-JUNCTIONS STT-MRAM
Online Access:	https://scholarbank.nus.edu.sg/handle/10635/156174
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Institution:	National University of Singapore
Language:	English

id	sg-nus-scholar.10635-156174
record_format	dspace
spelling	sg-nus-scholar.10635-1561742023-09-21T08:45:03Z Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells Fong, Xuanyao Kim, Yusung Choday, Sri Harsha Roy, Kaushik DEPT OF ELECTRICAL & COMPUTER ENGG Science & Technology Technology Computer Science, Hardware & Architecture Engineering, Electrical & Electronic Computer Science Engineering Bit-cell optimization failure mitigation magnetic tunneling junction (MTJ) spin-transfer torque magnetic RAM (STT-MRAM) MAGNETIC TUNNEL-JUNCTIONS STT-MRAM 10.1109/TVLSI.2013.2239671 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 22 2 384-395 2019-07-03T03:20:43Z 2019-07-03T03:20:43Z 2014-02-01 2019-07-03T02:56:48Z Article Fong, Xuanyao, Kim, Yusung, Choday, Sri Harsha, Roy, Kaushik (2014-02-01). Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 22 (2) : 384-395. ScholarBank@NUS Repository. https://doi.org/10.1109/TVLSI.2013.2239671 1063-8210 1557-9999 https://scholarbank.nus.edu.sg/handle/10635/156174 en IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC Elements
institution	National University of Singapore
building	NUS Library
continent	Asia
country	Singapore Singapore
content_provider	NUS Library
collection	ScholarBank@NUS
language	English
topic	Science & Technology Technology Computer Science, Hardware & Architecture Engineering, Electrical & Electronic Computer Science Engineering Bit-cell optimization failure mitigation magnetic tunneling junction (MTJ) spin-transfer torque magnetic RAM (STT-MRAM) MAGNETIC TUNNEL-JUNCTIONS STT-MRAM
spellingShingle	Science & Technology Technology Computer Science, Hardware & Architecture Engineering, Electrical & Electronic Computer Science Engineering Bit-cell optimization failure mitigation magnetic tunneling junction (MTJ) spin-transfer torque magnetic RAM (STT-MRAM) MAGNETIC TUNNEL-JUNCTIONS STT-MRAM Fong, Xuanyao Kim, Yusung Choday, Sri Harsha Roy, Kaushik Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells
description	10.1109/TVLSI.2013.2239671
author2	DEPT OF ELECTRICAL & COMPUTER ENGG
author_facet	DEPT OF ELECTRICAL & COMPUTER ENGG Fong, Xuanyao Kim, Yusung Choday, Sri Harsha Roy, Kaushik
format	Article
author	Fong, Xuanyao Kim, Yusung Choday, Sri Harsha Roy, Kaushik
author_sort	Fong, Xuanyao
title	Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells
title_short	Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells
title_full	Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells
title_fullStr	Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells
title_full_unstemmed	Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells
title_sort	failure mitigation techniques for 1t-1mtj spin-transfer torque mram bit-cells
publisher	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
publishDate	2019
url	https://scholarbank.nus.edu.sg/handle/10635/156174
_version_	1778169136780673024

Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells

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