Sub-10 nm Scalability of Junctionless FETs Using a Ground Plane in High-K BOX: A Simulation Study

10.1109/ACCESS.2020.3012579

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Main Authors: Jain, A.K., Kumar, M.J.
Other Authors: ELECTRICAL AND COMPUTER ENGINEERING
Format: Article
Published: Institute of Electrical and Electronics Engineers Inc. 2021
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Online Access:https://scholarbank.nus.edu.sg/handle/10635/198377
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spelling sg-nus-scholar.10635-1983772024-11-09T13:11:34Z Sub-10 nm Scalability of Junctionless FETs Using a Ground Plane in High-K BOX: A Simulation Study Jain, A.K. Kumar, M.J. ELECTRICAL AND COMPUTER ENGINEERING Band-to-band tunneling (BTBT) drain induced barrier lowering (DIBL) gate induced drain leakage (GIDL) Junctionless FET (JLFET) parasitic bipolar junction transistor (BJT) 10.1109/ACCESS.2020.3012579 IEEE Access 8 137540-137548 2021-08-20T02:48:52Z 2021-08-20T02:48:52Z 2020 Article Jain, A.K., Kumar, M.J. (2020). Sub-10 nm Scalability of Junctionless FETs Using a Ground Plane in High-K BOX: A Simulation Study. IEEE Access 8 : 137540-137548. ScholarBank@NUS Repository. https://doi.org/10.1109/ACCESS.2020.3012579 21693536 https://scholarbank.nus.edu.sg/handle/10635/198377 Institute of Electrical and Electronics Engineers Inc. Scopus OA2020
institution National University of Singapore
building NUS Library
continent Asia
country Singapore
Singapore
content_provider NUS Library
collection ScholarBank@NUS
topic Band-to-band tunneling (BTBT)
drain induced barrier lowering (DIBL)
gate induced drain leakage (GIDL)
Junctionless FET (JLFET)
parasitic bipolar junction transistor (BJT)
spellingShingle Band-to-band tunneling (BTBT)
drain induced barrier lowering (DIBL)
gate induced drain leakage (GIDL)
Junctionless FET (JLFET)
parasitic bipolar junction transistor (BJT)
Jain, A.K.
Kumar, M.J.
Sub-10 nm Scalability of Junctionless FETs Using a Ground Plane in High-K BOX: A Simulation Study
description 10.1109/ACCESS.2020.3012579
author2 ELECTRICAL AND COMPUTER ENGINEERING
author_facet ELECTRICAL AND COMPUTER ENGINEERING
Jain, A.K.
Kumar, M.J.
format Article
author Jain, A.K.
Kumar, M.J.
author_sort Jain, A.K.
title Sub-10 nm Scalability of Junctionless FETs Using a Ground Plane in High-K BOX: A Simulation Study
title_short Sub-10 nm Scalability of Junctionless FETs Using a Ground Plane in High-K BOX: A Simulation Study
title_full Sub-10 nm Scalability of Junctionless FETs Using a Ground Plane in High-K BOX: A Simulation Study
title_fullStr Sub-10 nm Scalability of Junctionless FETs Using a Ground Plane in High-K BOX: A Simulation Study
title_full_unstemmed Sub-10 nm Scalability of Junctionless FETs Using a Ground Plane in High-K BOX: A Simulation Study
title_sort sub-10 nm scalability of junctionless fets using a ground plane in high-k box: a simulation study
publisher Institute of Electrical and Electronics Engineers Inc.
publishDate 2021
url https://scholarbank.nus.edu.sg/handle/10635/198377
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