Interface design for rationally clocked GALS systems
10.1109/ASYNC.2006.19
Saved in:
Main Authors: | Mekie, J., Chakraborty, S., Venkataramani, G., Thiagarajan, P.S., Sharma, D.K. |
---|---|
Other Authors: | COMPUTER SCIENCE |
Format: | Conference or Workshop Item |
Published: |
2013
|
Online Access: | http://scholarbank.nus.edu.sg/handle/10635/40358 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | National University of Singapore |
Similar Items
-
The GalNAc-T activation (GAlA) pathway: Drivers and markers
by: Chia, J., et al.
Published: (2021) -
Test methods for gals processor
by: Ye Myat Thu.
Published: (2011) -
sFPGA2 - A scalable gals FPGA architecture and design methodology
by: Syed, R., et al.
Published: (2014) -
Mediator acts upstream of the transcriptional activator Gal4
by: Ang K., et al.
Published: (2020) -
Rational Design of Materials Interface for Efficient Capture of Circulating Tumor Cells
by: Li, Y.-Q, et al.
Published: (2020)