Test bench modeling and characterization for fine pitch wafer level packaged devices

Proceedings of 6th Electronics Packaging Technology Conference, EPTC 2004

Saved in:

Bibliographic Details
Main Authors:	Jayabalan, J., Mihai, R.D., Tan, J.P.H., Iyer, M.K., Leong, O.B., Seng, L.M.
Other Authors:	MECHANICAL ENGINEERING
Format:	Conference or Workshop Item
Published:	2014
Subjects:	Fine pitch Interconnect modeling Multi-gigahertz test Wafer level package
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/71958
Tags:	Add Tag No Tags, Be the first to tag this record!
Institution:	National University of Singapore

id	sg-nus-scholar.10635-71958
record_format	dspace
spelling	sg-nus-scholar.10635-719582015-01-07T02:55:33Z Test bench modeling and characterization for fine pitch wafer level packaged devices Jayabalan, J. Mihai, R.D. Tan, J.P.H. Iyer, M.K. Leong, O.B. Seng, L.M. MECHANICAL ENGINEERING ELECTRICAL & COMPUTER ENGINEERING Fine pitch Interconnect modeling Multi-gigahertz test Wafer level package Proceedings of 6th Electronics Packaging Technology Conference, EPTC 2004 502-505 2014-06-19T03:29:49Z 2014-06-19T03:29:49Z 2004 Conference Paper Jayabalan, J.,Mihai, R.D.,Tan, J.P.H.,Iyer, M.K.,Leong, O.B.,Seng, L.M. (2004). Test bench modeling and characterization for fine pitch wafer level packaged devices. Proceedings of 6th Electronics Packaging Technology Conference, EPTC 2004 : 502-505. ScholarBank@NUS Repository. 0780388216 http://scholarbank.nus.edu.sg/handle/10635/71958 NOT_IN_WOS Scopus
institution	National University of Singapore
building	NUS Library
country	Singapore
collection	ScholarBank@NUS
topic	Fine pitch Interconnect modeling Multi-gigahertz test Wafer level package
spellingShingle	Fine pitch Interconnect modeling Multi-gigahertz test Wafer level package Jayabalan, J. Mihai, R.D. Tan, J.P.H. Iyer, M.K. Leong, O.B. Seng, L.M. Test bench modeling and characterization for fine pitch wafer level packaged devices
description	Proceedings of 6th Electronics Packaging Technology Conference, EPTC 2004
author2	MECHANICAL ENGINEERING
author_facet	MECHANICAL ENGINEERING Jayabalan, J. Mihai, R.D. Tan, J.P.H. Iyer, M.K. Leong, O.B. Seng, L.M.
format	Conference or Workshop Item
author	Jayabalan, J. Mihai, R.D. Tan, J.P.H. Iyer, M.K. Leong, O.B. Seng, L.M.
author_sort	Jayabalan, J.
title	Test bench modeling and characterization for fine pitch wafer level packaged devices
title_short	Test bench modeling and characterization for fine pitch wafer level packaged devices
title_full	Test bench modeling and characterization for fine pitch wafer level packaged devices
title_fullStr	Test bench modeling and characterization for fine pitch wafer level packaged devices
title_full_unstemmed	Test bench modeling and characterization for fine pitch wafer level packaged devices
title_sort	test bench modeling and characterization for fine pitch wafer level packaged devices
publishDate	2014
url	http://scholarbank.nus.edu.sg/handle/10635/71958
_version_	1681087478367256576

Test bench modeling and characterization for fine pitch wafer level packaged devices

Similar Items