Test bench modeling and characterization for fine pitch wafer level packaged devices

• Main Authors: Jayabalan, J., Mihai, R.D., Tan, J.P.H., Iyer, M.K., Leong, O.B., Seng, L.M.
• Other Authors: MECHANICAL ENGINEERING
• Format: Conference or Workshop Item
• Published: 2014
• Subjects: Fine pitch; Interconnect modeling; Multi-gigahertz test; Wafer level package
• Online Access: http://scholarbank.nus.edu.sg/handle/10635/71958
• Institution: National University of Singapore

Proceedings of 6th Electronics Packaging Technology Conference, EPTC 2004