An accurate delay model for BiCMOS logic gates

International Symposium on IC Technology, Systems and Applications

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Bibliographic Details
Main Authors:	Samudra, G., Zhao, B.
Other Authors:	ELECTRICAL ENGINEERING
Format:	Conference or Workshop Item
Published:	2014
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/72474
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Institution:	National University of Singapore

id	sg-nus-scholar.10635-72474
record_format	dspace
spelling	sg-nus-scholar.10635-724742024-11-09T07:32:49Z An accurate delay model for BiCMOS logic gates Samudra, G. Zhao, B. ELECTRICAL ENGINEERING International Symposium on IC Technology, Systems and Applications 8 545-548 2014-06-19T05:08:28Z 2014-06-19T05:08:28Z 1999 Conference Paper Samudra, G.,Zhao, B. (1999). An accurate delay model for BiCMOS logic gates. International Symposium on IC Technology, Systems and Applications 8 : 545-548. ScholarBank@NUS Repository. http://scholarbank.nus.edu.sg/handle/10635/72474 NOT_IN_WOS Scopus
institution	National University of Singapore
building	NUS Library
continent	Asia
country	Singapore Singapore
content_provider	NUS Library
collection	ScholarBank@NUS
description	International Symposium on IC Technology, Systems and Applications
author2	ELECTRICAL ENGINEERING
author_facet	ELECTRICAL ENGINEERING Samudra, G. Zhao, B.
format	Conference or Workshop Item
author	Samudra, G. Zhao, B.
spellingShingle	Samudra, G. Zhao, B. An accurate delay model for BiCMOS logic gates
author_sort	Samudra, G.
title	An accurate delay model for BiCMOS logic gates
title_short	An accurate delay model for BiCMOS logic gates
title_full	An accurate delay model for BiCMOS logic gates
title_fullStr	An accurate delay model for BiCMOS logic gates
title_full_unstemmed	An accurate delay model for BiCMOS logic gates
title_sort	accurate delay model for bicmos logic gates
publishDate	2014
url	http://scholarbank.nus.edu.sg/handle/10635/72474
_version_	1821214733248757760

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