Comparative study of charge trapping effects in LDD surface-channel and buried-channel PMOS transistors using charge profiling and threshold voltage shift measurements

Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

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Main Authors:	Kok, C.K., Chew, W.C., Chim, W.K., Chan, D.S.H., Leang, S.E.
Other Authors:	ELECTRICAL ENGINEERING
Format:	Conference or Workshop Item
Published:	2014
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/72523
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Institution:	National University of Singapore

id	sg-nus-scholar.10635-72523
record_format	dspace
spelling	sg-nus-scholar.10635-725232015-01-08T19:07:07Z Comparative study of charge trapping effects in LDD surface-channel and buried-channel PMOS transistors using charge profiling and threshold voltage shift measurements Kok, C.K. Chew, W.C. Chim, W.K. Chan, D.S.H. Leang, S.E. ELECTRICAL ENGINEERING Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 200-205 00234 2014-06-19T05:09:00Z 2014-06-19T05:09:00Z 1999 Conference Paper Kok, C.K.,Chew, W.C.,Chim, W.K.,Chan, D.S.H.,Leang, S.E. (1999). Comparative study of charge trapping effects in LDD surface-channel and buried-channel PMOS transistors using charge profiling and threshold voltage shift measurements. Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA : 200-205. ScholarBank@NUS Repository. http://scholarbank.nus.edu.sg/handle/10635/72523 NOT_IN_WOS Scopus
institution	National University of Singapore
building	NUS Library
country	Singapore
collection	ScholarBank@NUS
description	Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
author2	ELECTRICAL ENGINEERING
author_facet	ELECTRICAL ENGINEERING Kok, C.K. Chew, W.C. Chim, W.K. Chan, D.S.H. Leang, S.E.
format	Conference or Workshop Item
author	Kok, C.K. Chew, W.C. Chim, W.K. Chan, D.S.H. Leang, S.E.
spellingShingle	Kok, C.K. Chew, W.C. Chim, W.K. Chan, D.S.H. Leang, S.E. Comparative study of charge trapping effects in LDD surface-channel and buried-channel PMOS transistors using charge profiling and threshold voltage shift measurements
author_sort	Kok, C.K.
title	Comparative study of charge trapping effects in LDD surface-channel and buried-channel PMOS transistors using charge profiling and threshold voltage shift measurements
title_short	Comparative study of charge trapping effects in LDD surface-channel and buried-channel PMOS transistors using charge profiling and threshold voltage shift measurements
title_full	Comparative study of charge trapping effects in LDD surface-channel and buried-channel PMOS transistors using charge profiling and threshold voltage shift measurements
title_fullStr	Comparative study of charge trapping effects in LDD surface-channel and buried-channel PMOS transistors using charge profiling and threshold voltage shift measurements
title_full_unstemmed	Comparative study of charge trapping effects in LDD surface-channel and buried-channel PMOS transistors using charge profiling and threshold voltage shift measurements
title_sort	comparative study of charge trapping effects in ldd surface-channel and buried-channel pmos transistors using charge profiling and threshold voltage shift measurements
publishDate	2014
url	http://scholarbank.nus.edu.sg/handle/10635/72523
_version_	1681087581266116608

Comparative study of charge trapping effects in LDD surface-channel and buried-channel PMOS transistors using charge profiling and threshold voltage shift measurements

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